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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright cirrus logic, inc. 2001 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com features 28-pin cason package 1.8 to 3.3 volt supply 24-bit conversion / 96 khz sample rate 96 db adc/dac dynamic range at 3 v supply -88/-85 db adc/dac thd+n 19 mw playback power consumption @ 1.8 v microphone or line input amplifier with up to 32db of gain 2:1 stereo mux digital volume control on inputs and outputs ? 96 db attenuation, 1 db step size digital bass and treble boost on outputs ? selectable corner frequencies dynamic range compression and limiting de-emphasis for 32 khz, 44.1 khz, and 48 khz headphone amplifier ? 26 mw power output into 16 w load @ 3.0v supply ? -80 db thd+n ? 34 db analog attenuation and mute atapi mixing functions description the CS42L50 is a highly integrated, 24-bit, 96 khz audio codec. this device is based on delta-sigma modulation allowing infinite adjustment of the sample rate between 8 khz and 100 khz simply by changing the master clock frequency. t he cs 4 2l 5 0 c o n t a i ns a 2:1 s t e r eo mu x , p r o g r a m m ab l e analog gain control, and digital attenuation on the analog inputs. the output d/a converters include digital bass and treble boost, dynamic range compression, limiting, mixing, volume control and de-emphasis. the CS42L50 operates from a +1.8 v to +3.3 v supply. these features are ideal for portable mp3 and md re- corders, cd and dvd recorders, digital camcorders, and other portable systems that require extremely low power consumption in a minimal amount of space. ordering information CS42L50-kn 28-pin cason, -10 to 70 c cdb42l50 evaluation board i i scl sda control port digital volume control bass/treble boost compression limiting analog filter analog filter hp_a hp_b aout_a aout_b rst lrck sclk sdin serial port de-emphasis digital filters ? dac ? dac headphone amplifier analog volume control mclk analog volume control line amplifier compensation g a i n va vl mutec ain_l1 ain_l2 ain_r1 ain_r2 sdout mux mux adc adc digital filters attenuator 0-96 db attenuator 0-96 db 12 db gain gain 12 db CS42L50 low voltage, stereo codec with headphone amp aug ?01 ds544pp1
CS42L50 2 ds544pp1 table of contents 1. characteristics/specifications ................................................................................. 5 analog input characteristics .................................................................................... 5 analog output characteristics ................................................................................ 7 power and thermal characteristics..................................................................... 10 digital characteristics ............................................................................................... 11 absolute maximum ratings ......................................................................................... 11 recommended operating conditions ..................................................................... 11 switching characteristics ........................................................................................ 12 switching characteristics - control port......................................................... 14 2. typical connection diagram ....................................................................................... 15 3. register quick reference ........................................................................................... 16 4. register description ..................................................................................................... 18 4.1 adc (address 0010000) .................................................................................................. 18 4.1.1 i/o and power control (address 01h) .......................................................................... 18 4.1.2 20db gain boost (boost) .......................................................................................... 18 4.1.3 analog input multiplexer (ainmux) ............................................................................... 18 4.1.4 power down (pdn)........................................................................................................ 1 8 4.1.5 control port enable (cp_en) ........................................................................................ 18 4.1.6 interface control (address 02h) .................................................................................... 19 4.1.7 master clock divide (mclkdiv)................................................................................... 19 4.1.8 master clock ratio (ratio) ......................................................................................... 19 4.1.9 master mode (master)............................................................................................... 19 4.1.10 digital interface format (dif) ..................................................................................... 19 4.1.11 analog i/o control (address 03h) ............................................................................... 20 4.1.12 left/right channel mute (mute)............................................................................... 20 4.1.13 soft ramp and zero cross enable (soft/zc) ......................................................... 20 4.1.14 independent volume control enable (indvc) .......................................................... 21 4.1.15 left channel volume = right channel volume (l=r) ............................................... 21 4.1.16 high-pass filter freeze (hpfreeze)....................................................................... 21 4.1.17 volume control: left channel (address 04h) & right channel (address 05h) ............ 22 4.1.18 left/right analog gain (address 06h) ........................................................................ 22 4.1.19 clip detection status (address 07h) .......................................................................... 23 4.2 dac (address = 0010001) ............................................................................................... 23 4.2.1 power and muting control (address 01h) .................................................................... 23 4.2.2 auto-mute (amute) ..................................................................................................... 23 4.2.3 soft ramp and zero cross control (szc) ..................................................................... 23 4.2.4 power down headphone amplifier (pdnhp) ................................................................ 24 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm purchase of i 2 c components of cirrus logic, inc., or one of its sublicensed associated companies conveys a license under the ph ilips i 2 c patent rights to use those components in a standard i 2 c system. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product information de- scribes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensu re that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? withou t warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information b eing relied on is current and complete. all prod- ucts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertain ing to warranty, patent infringement, and limitation of liability. no res ponsib ility is assumed by cirrus logic, inc. for the use of this information, including use of this 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appearing in this document may be trademarks or serv ice marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com .
CS42L50 ds544pp1 3 4.2.5 power down line amplifier (pdnln) ............................................................................ 24 4.2.6 power down (pdn) ....................................................................................................... 24 4.2.7 control port enable (cp_en) ........................................................................................ 24 4.2.8 channel a analog headphone attenuation control (address 02h) (hvola) .............. 25 4.2.9 channel b analog headphone attenuation control (address 03h) (hvolb) .............. 25 4.2.10 channel a digital volume control (address 04h) (dvola) ....................................... 25 4.2.11 channel b digital volume control (address 05h) (dvolb) ....................................... 25 4.2.12 tone control (address 06h)........................................................................................ 26 4.2.13 bass boost level (bb)................................................................................................. 26 4.2.14 treble boost level (tb)............................................................................................... 26 4.2.15 mode control (address 07h)....................................................................................... 27 4.2.16 bass boost corner frequency (bbcf) ....................................................................... 27 4.2.17 treble boost corner frequency (tbcf) ..................................................................... 27 4.2.18 channel a volume = channel b volume (a=b) .......................................................... 27 4.2.19 de-emphasis control (dem) ....................................................................................... 28 4.2.20 digital volume control bypass (vcbyp) .................................................................... 28 4.2.21 volume and mixing control (address 0ah)................................................................. 28 4.2.22 tone control mode (tc).............................................................................................. 28 4.2.23 tone control enable (tc_en) .................................................................................... 28 4.2.24 atapi channel mixing and muting (atapi)................................................................ 29 4.2.25 mode control 2 (address 0bh) ................................................................................... 29 4.2.26 master clock divide enable (mclkdiv) ..................................................................... 29 4.2.27 line amplifier gain compensation (line)................................................................... 29 4.2.28 digital interface format (dif) ...................................................................................... 30 5. pin descriptions ........................................................................................................... .... 31 6. applications ............................................................................................................... ....... 33 6.1 grounding and power supply decoupling ....................................................................... 33 6.2 clock modes ............................................................................................................... ..... 33 6.3 ep73xx serial port interface ........................................................................................... 33 6.4 de-emphasis ............................................................................................................... .... 33 6.5 recommended power-up sequence ............................................................................... 33 6.6 optional external headphone mute ................................................................................ 33 7. control port interface ............................................................................................... 33 7.1 memory address pointer (map) ...................................................................................... 35 7.2 incr (auto map increment enable) ................................................................................. 35 7.3 map0-3 (memory address pointer).................................................................................. 35 8. parameter definitions ................................................................................................... 44 9. references ................................................................................................................. ........ 44 10. package dimensions ..................................................................................................... 45 list of figures figure 1. sclk to lrck and sdin, slave mode .................................................... 13 figure 2. sclk to lrck and sdin, master mode .................................................. 13 figure 3. control port timing - i 2 c? ......................................................................... 14 figure 4. CS42L50 typical connection diagram .................................................... 15 figure 5. control port timing .................................................................................. 35 figure 6. decimation filter single speed stopband rejection ............................... 36 figure 7. decimation filter single speed transition band ...................................... 36 figure 8. decimation filter single speed transition band (detail) ......................... 36 figure 9. decimation filter single speed passband ripple ................................... 36 figure 10.decimation filter double speed stopband rejection .............................. 36 figure 11.decimation filter double speed transition band .................................... 36 figure 12.decimation filter double speed transition band (detail) ........................ 37
CS42L50 4 ds544pp1 figure 13.decimation filter double speed passband ripple .................................. 37 figure 14.interpolation filter single speed stopband rejection .............................. 38 figure 15.interpolation filter single speed transition band .................................... 38 figure 16.interpolation filter single speed transition band (detail) ....................... 38 figure 17.interpolation filter single speed passband ripple .................................. 38 figure 18.interpolation filter double speed stopband rejection ............................ 38 figure 19.interpolation filter double speed transition band ................................... 38 figure 20.interpolation filter double speed transition band (detail) ...................... 39 figure 21.interpolation filter double speed passband ripple ................................. 39 figure 22.line input test circuit .............................................................................. 39 figure 23.line output test load .............................................................................. 40 figure 24.headphone output test load .................................................................. 40 figure 25.left justified, up to 24-bit data ................................................................. 41 figure 26.right justified, 16-bit data ........................................................................ 41 figure 27.right justified, 24-bit data ........................................................................ 41 figure 28.right justified, 18-bit data ........................................................................ 42 figure 29.right justified, 20-bit data ........................................................................ 42 figure 30.i2s, up to 24-bit data ................................................................................ 42 figure 31.de-emphasis curve ................................................................................. 43 figure 32.atapi block diagram ............................................................................... 43 figure 33.package dimensions ................................................................................ 45 figure 34.package top and side views .................................................................. 46 figure 35.package bottom view .............................................................................. 47 list of tables table 1. example analog volume settings ...................................................................................25 table 2. example digital volume settings ....................................................................................26 table 3. example bass boost settings .........................................................................................26 table 4. example treble boost settings .......................................................................................27 table 5. atapi decode.......................................................................................................... .......29 table 6. digital interface format .............................................................................................. .....30
CS42L50 ds544pp1 5 1. characteristics/specifications analog input characteristics (t a = 25 c; gnd = 0 v logic "1" = vl = 1.8 v; logic "0" = gnd = 0 v; mclk = 12.288 mhz; fs for single speed mode = 48 khz, sclk = 3.072 mhz, fs for double speed mode = 96 khz, sclk = 6.144 mhz; measurement bandwidth 10 hz to 20 khz, unless otherwise specified. input is 997hz sine wave.) parameter symbol single speed mode double speed mode unit min typ max min typ max analog input characteristics for va = 1.8 v dynamic range a-weighted unweighted tbd tbd 93 90 - - tbd tbd 94 91 - - db db total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -70 -30 -86 -68 -28 tbd - - - - - - - - - - - -88 -71 -31 -86 -68 -28 tbd - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 90 87 85 82 - - - - - - - - 89 86 86 83 - - - - db db db db total harmonic distortion + noise (pga on)* (note 1) 0 db gain, 18 to 24-bit -1 db 12 db gain, 18 to 24-bit -1 db thd+n - - 85 83 - - - - 84 82 - - db db analog input characteristics for va = 3.0 v dynamic range a-weighted unweighted tbd tbd 96 93 - - tbd tbd 98 95 - - db db total harmonic distortion + noise (note 1) 18 to 24-bit -1 db -20 db -60 db 16-bit -1 db -20 db -60 db thd+n - - - - - - -88 -73 -33 -86 -68 -28 tbd - - - - - - - - - - - -85 -75 -35 -83 -65 -28 tbd - - - - - db db db db db db dynamic range (pga on)* 0 db gain a-weighted unweighted 12 db gain a-weighted unweighted - - - - 93 90 88 85 - - - - - - - - 92 89 89 86 - - - - db db db db total harmonic distortion + noise (pga on)* (note 1) 0 db gain, 18 to 24-bit -1 db 12 db gain, 18 to 24-bit -1 db thd+n - - 78 73 - - - - 77 76 - - db db *pga : programmable gain amplifier
CS42L50 6 ds544pp1 analog input characteristics for va = 1.8 - 3.3v interchannel isolation 1 khz - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db offset error (with hpf active) - - 0 - - 0 lsb full scale input voltage tbd va/3.6 tbd tbd va/3.6 tbd vrms gain drift - 100 - - 100 - ppm/c input resistance 10 - - 10 - - k ? input capacitance - - 15 - - 15 pf programmable gain characteristics gain step size - 1.0 - - 1.0 - db absolute gain step error - - tbd - - tbd db a/d decimation filter characteristics (note 2) passband (note 3) 0 - 23.5 0 - 47.5 khz passband ripple -0.08 - +0.17 -0.09 - 0 db stopband (note 3) 27.5 - - 64.1 - - khz stopband attenuation (note 4) -60.3 - - -48.4 - - db group delay (fs = output sample rate)(note 5) t gd - 10/fs - - 2.7/fs - s group delay variation vs. frequency ? t gd - - 0.03 - - 0.007 s high pass filter characteristics frequency response -3 db (note 2) -0.1 db - - 3.7 24.2 - - - - 3.7 24.2 - - hz hz phase deviation @ 20 hz (note 2) - 10 - - 10 - degree passband ripple (note 2) - - 0.17 - - 0.09 db parameter symbol single speed mode double speed mode unit min typ max min typ max *pga : programmable gain amplifier
CS42L50 ds544pp1 7 analog output characteristics (t a = 25 c; logic "1" = vl = 1.8 v; logic "0" = gnd = 0 v; full-scale output sine wave, 997 hz; mclk = 12.288 mhz; measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for single speed mode = 48 khz, sclk = 3.072 mhz. fs for double speed mode = 96 khz, sclk = 6.144 mhz. test load r l =10k ? , c l = 10 pf (see figure 23) for line out, r l =16 ? , c l = 10 pf (see figure 24) for headphone out. notes: 1. referenced to typical full-scale input voltage. 2. filter response is not tested but is guaranteed by design. 3. filter characteristics scale with output sample rate. for output sample rates, fs, other than 48 khz, the 0.01 db passband edge is 0.4535x fs and the stopband edge is 0.625x fs. 4. the analog modulator samples the input at 6.144 mhz for an fs equal to 48 khz. there is no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 mhz 21.8 khz where n = 0,1,2,3...). 5. group delay for fs = 48 khz, t gd = 10/48 khz = 208 s. 6. one-half lsb of triangular pdf dither is added to data. parameter single speed mode double speed mode symbol min typ max min typ max unit line output dynamic performance for va = 1.8 v dynamic range (note 6) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 91 94 89 92 - - - - tbd tbd - - 89 92 87 90 - - - - db db db db total harmonic distortion + noise (note 6) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -80 -71 -31 -78 -69 -29 tbd - - - - - - - - - - - -80 -69 -29 -78 -67 -27 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db headphone output dynamic performance for va = va_hp = 1.8 v dynamic range (note 6) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 88 91 86 89 - - - - tbd tbd - - 88 91 86 89 - - - - db db db db total harmonic distortion + noise (note 6) 18 to 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - -82 -68 -28 -80 -66 -26 tbd - - - - - - - - - - - -85 -68 -28 -83 -66 -26 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 66 - - 66 - db
CS42L50 8 ds544pp1 analog output characteristics (continued) parameter single speed mode double speed mode symbol min typ max min typ max unit line output dynamic performance for va = 3.0 v dynamic range (note 6) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 93 96 91 94 - - - - tbd tbd - - 93 96 91 94 - - - - db db db db total harmonic distortion + noise (note 6) 18 to 24 bit 0db -20db -60db 16-bit 0db -20db -60db thd+n - - - - - - -85 -73 -33 -83 -71 -31 tbd - - - - - - - - - - - -85 -73 -33 -83 -71 -31 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 100 - - 100 - db headphone output dynamic performance for va = va_hp = 3.0 v dynamic range (note 6) 18 to 24-bit unweighted a-weighted 16-bit unweighted a-weighted tbd tbd - - 90 93 88 91 - - - - tbd tbd - - 90 93 88 91 - - - - db db db db total harmonic distortion + noise (note 6) 18 to 24 bit 0db -20db -60db 16-bit 0db -20db -60db thd+n - - - - - - -76 -70 -30 -74 -68 -28 tbd - - - - - - - - - - - -73 -70 -30 -71 -68 -28 tbd - - - - - db db db db db db interchannel isolation (1 khz) - 66 - - 66 - db
CS42L50 ds544pp1 9 analog output characteristics (continued) notes: 7. see section 4.2.7 for details. 8. filter response is not tested but is guaranteed by design. 9. response is clock dependent and will scale with fs. note that the response plots (figures 14 through 21) have been normalized to fs and can be de-normalized by multiplying the x-axis scale by fs. 10. referenced to a 1 khz, full-scale sine wave. 11. for single speed mode, the measurement bandwidth is 0.5465 fs to 3 fs. for double speed mode, the measurement bandwidth is 0.577 fs to 1.4 fs. 12. de-emphasis is not available in double speed mode. parameters symbol min typ max units analog output full scale line output voltage (note 7) v fs_line tbd g x va tbd vpp line output quiescent voltage v q_line - 0.5 x va_line - vdc full scale headphone output voltage v fs_hp tbd 0.55 x va tbd vpp headphone output quiescent voltage v q_hp - 0.5 x va_hp - vdc interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c maximum line output ac-current va=1.8 v va=3.0 v i line - - 0.1 0.15 - - ma ma maximum headphone output va=va_hp=1.8 v ac-current va=va_hp=3.0 v i hp - - 31 52 - - ma ma parameter single speed mode double speed mode symbol min typ max min typ max unit combined digital and on-chip analog filter response (note 8) passband (note 9) to -0.05 db corner to -0.1 db corner to -3 db corner 0 - 0 - - - .4535 - .4998 - 0 0 - - - - .4426 .4984 fs fs fs frequency response 10 hz to 20 khz (note 10) -.02 - +.08 0 - +0.11 db stopband .5465 - - .577 - - fs stopband attenuation (note 11) 50 - - 55 - - db group delay tgd - 9/fs - - 4/fs - s passband group delay deviation 0 - 40 khz 0 - 20 khz - - - 0.36/fs - - - - 1.39/fs 0.23/fs - - s s de-emphasis error fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - +.2/-.1 +.05/-.14 +0/-.22 (note 12) db db db
CS42L50 10 ds544pp1 power and thermal characteristics (gnd = 0 v; all voltages with respect to ground. all measurements taken with all zeros input and open outputs, unless otherwise specified.) notes: 13. power down mode is defined as rst = lo with all clocks and data lines held static. 14. valid with the recommended capacitor values on filt+_adc, filt+_dac, vq_dac, and vq_adc as shown in figure 4. increasing the capacitance will also increase the psrr. note that care should be taken when selecting capacitor type, as any leakage current in excess of 1.0 a will cause degradation in analog performance. a small ceramic capacitor in parallel with a larger electrolytic is recommended. parameters symbol min typ max units power supplies power supply current- va=1.8 v normal operation va_hp=1.8 v vl=1.8 v i a i a_hp i d_l - - - 13.3 1.5 154 - - - ma ma a power supply current- va=3.0 v normal operation va_hp=3.0 v vl=3.0 v i a i a_hp i d_l - - - 20 1.5 270 - - - ma ma a power supply current- all supplies=1.8 v power down mode (note 13) all supplies =3.0v - - 150 350 - - a a total power dissipation- all supplies=1.8 v normal operation all supplies=3.0 v - - 27 65 tbd tbd mw mw maximum headphone power dissipation (1 khz full-scale sine wave va=1.8 v into 16 ohm load) va=3.0 v - - 15 26 - - mw mw package thermal resistance ja -55-c/watt power supply rejection ratio (note 14) (1 khz) (60 hz) psrr - - 60 40 - - db db
CS42L50 ds544pp1 11 digital characteristics (t a = 25 c; vl = 1.7 v - 3.3 v; gnd = 0 v) absolute maximum ratings (gnd = 0v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v; all voltages with respect to ground.) notes: 15. va and va_hp should be tied to the same supply as shown in figure 4. parameters symbol min typ max units high-level input voltage v ih 0.7 x vl - - v low-level input voltage v il - - 0.3 x vl v input leakage current i in --10 a high-level output voltage v oh 0.7 x vl - - v low-level output voltage v ol - - 0.3 x vl v input capacitance - 8 - pf maximum mutec drive capability va=1.8 v va=3.0 v - - tbd 3 - - ma ma mutec high-level output voltage - va - v mutec low-level output voltage - 0 - v parameters symbol min max units dc power supplies: analog&headphone digital i/o va&va_hp vl -0.3 -0.3 4.0 4.0 v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units ambient temperature t a -10 - 70 c dc power supplies: analog&headphone (note 15) digital i/o va&va_hp vl 1.7 1.7 - - 3.6 3.6 v v
CS42L50 12 ds544pp1 switching characteristics (t a = -10 to 70 c; va = 1.7 v - 3.3 v; inputs: logic 0 = gnd, logic 1 = vl, c l = 20 pf) 16. there must be exactly 32, 48, 64, or 128 sclk periods per lrck transition. parameters symbol min typ max units input sample rate single speed mode double speed mode fs fs 2 50 - - 50 100 khz khz mclk pulse width high mclk/lrck = 1024 8 - - ns mclk pulse width low mclk/lrck = 1024 8 - - ns mclk pulse width high mclk/lrck = 768 10 - - ns mclk pulse width low mclk/lrck = 768 10 - - ns mclk pulse width high mclk/lrck = 512 15 - - ns mclk pulse width low mclk/lrck = 512 15 - - ns mclk pulse width high mclk / lrck = 384 or 192 25 - - ns mclk pulse width low mclk / lrck = 384 or 192 25 - - ns mclk pulse width high mclk / lrck = 256 or 128 35 - - ns mclk pulse width low mclk / lrck = 256 or 128 35 - - ns master mode sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdout valid t sdo 0 - 20 ns sclk duty cycle 40 50 60 % slave mode lrck duty cycle 40 50 60 % rise time of both lrck and sclk t r - - 10 ns fall time of both lrck and sclk t f - - 10 ns sclk period (note 16) single speed mode double speed mode t sclkw t sclkw - - - - ns ns sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdout valid single speed mode double speed mode t dss t dss - - - - ns ns 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 (512)fs 1 (256)fs
CS42L50 ds544pp1 13 sclk lrck sdin t sclkl t slrd t dss msb t sclkh t sclkw figure 1. sclk to lrck and sdin, slave mode sclk lrck sdin t slrd t sdo msb msb-1 figure 2. sclk to lrck and sdin, master mode
CS42L50 14 ds544pp1 switching characteristics - control port (t a = 25 c; vl = 1.7 v - 3.3 v; inputs: logic 0 = gnd, logic 1 = vl, c l = 30 pf) note: 17. data must be held for sufficient time to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl -100khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl t rc -25ns fall time of scl t fc -25ns rise time of sda t rd -1s fall time of sda t fd -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop s ta rt start stop repeated sda scl t irs rst figure 3. control port timing - i 2 c
CS42L50 ds544pp1 15 2. typical connection diagram c digital audio source CS42L50 1.0 f 0.1 f + + configuration gnd 1.0 f 17 1 k ? 16 ? headphones 4.7 h + 220 f 150 ? 0.47 f 150 ? 0.47 f ain_r1 150 ? 0.47 f 150 ? 0.47 f 1 k ? 4.7 h + 220 f 10 k ? + 3.3 f + 3.3 f 560 ? 10 k ? 560 ? c r l r l c mute circuit 0.1 f 1.0 f 0.1 f 1.0 f 1.0 f 1.0 f + + + + 0.1 f 0.1 f 1.8 to 3.3 v supply 1.8 to 3.3 v supply 15 5 4 12 14 16 23 8 7 19 13 21 11 28 20 24 25 18 10 3 6 27 26 9 22 1.0 nf 1.0 nf ain_l1 ain_l2 ain_r2 afltr afltl scl sda rst sdin sdout lrck sclk mclk filt+_adc aoutl aoutr mutec vq_dac filt+_dac ref_gnd vq_adc hp_a hp_b va_hp va vl r l + 560 4 f s (r l 560) c = 0. 1 f 0 0. 1 f 0 0. 1 f 0 0. 1 f 0 vl 2 1 figure 4. CS42L50 typical connection diagram
CS42L50 16 ds544pp1 3. register quick reference adc (address = 0010000) dac (address = 0010001) addr function 7 6 5 4 3 2 1 0 0h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 000 0000 0 1h i/o and power control reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en default 00 0 0001 0 2h interface control reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 default 000 0000 0 3h analog i/o control mutel muter szc1 szc0 reserved indvc l=r hpfreeze default 001 1000 0 4h left channel digital volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 0000 0 5h right channel digital volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default 000 0000 0 6h analog gain control lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 default 000 0000 0 7h clip detection status reserved reserved reserved reserved reserved reserved clip_l clip_r default 000 0000 0 addr function 7 6 5 4 3 2 1 0 0h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00000000 1h power and muting control amute szc1 szc0 reserved pdnhp pdnln pdn cp_en default 11 0 10010 2h channel a analog headphone attenuation control hvola7 hvola6 hvola5 hvola4 hvola3 hvola2 hvola1 hvola0 default 00000000 3h channel b analog headphone attenuation control hvolb7 hvolb6 hvolb5 hvolb4 hvolb3 hvolb2 hvolb1 hvolb0 default 00000000 4h channel a digital volume control dvola7 dvola6 dvola5 dvola4 dvola3 dvola2 dvola1 dvola0 default 00000000 5h channel b digital volume control dvolb7 dvolb6 dvolb5 dvolb4 dvolb3 dvolb2 dvolb1 dvolb0 default 00000000
CS42L50 ds544pp1 17 6h tone control bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 default 00000000 7h mode control bbcf1 bbcf0 tbcf1 tbcf0 a=b dem1 dem0 vcbyp default 00000000 8h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00010000 9h reserved reserved reserved reserved reserved reserved reserved reserved reserved default 00100000 ah volume and mixing control tc1 tc0 tc_en reserved atapi3 atapi2 atapi1 atapi0 default 00001001 bh mode control 2 mclkdiv line1 line0 reserved reserved dif2 dif1 dif0 default 00000000 addr function 7 6 5 4 3 2 1 0
CS42L50 18 ds544pp1 4. register description 4.1 adc (address = 0010000) 4.1.1 i/o and power control (address 01h) 4.1.2 20db gain boost (boost) default = 0 0 - disabled 1 - enabled function: applies a 20db digital gain to the input signal, regardless of the input path. 4.1.3 analog input multiplexer (ainmux) default = 00 00 - channel 1 direct to a/d 01 - channel 2 direct to a/d 10 - channel 2 through pga to a/d 11 - reserved function: t he a na l og in p ut m u l t i p le x er s e l e c t s the i n p ut c ha n nel as w e ll as the i n put p ath a s s o c i at e d w i th v a r i ous gain stages. 4.1.4 power down (pdn) default - 1 0 - disabled 1 - enabled function: the entire adc device will enter a low-power state whenever this function is activated. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation will begin. the con- tents of the control registers are retained when this mode is enabled. 4.1.5 control port enable (cp_en) default = 0 0 - disabled 1 - enabled function: the adc will enter control port mode when this bit is enabled. this bit must be set prior to writing to the control port. 76543210 reserved boost ainmux1 ainmux0 reserved reserved pdn cp_en 00000010
CS42L50 ds544pp1 19 4.1.6 interface control (address 02h) 4.1.7 master clock divide (mclkdiv) default = 0 0 - disabled 1 - enabled function: divides adc mclk by two prior to all other chip circuitry. 4.1.8 master clock ratio (ratio) default = 00 00 - 128x 01 - 192x 10 - 256x 11 - 384x function: sets the ratio of mclk to lrck for the adc. 4.1.9 master mode (master) default = 0 0 - slave mode 1 - master mode function: configures the CS42L50 for master or slave operation. 4.1.10 digital interface format (dif) default = 000 000 - i 2 s, up to 24-bit data, data valid on positive edge of sclk 001 - left justified, up to 24-bit data, data valid on positive edge of sclk 010 - reserved 011 - right justified, 16-bit data, data valid on positive edge of sclk 100 - right justifed, 24-bit data, data valid on positive edge of sclk 101 - right justified, 18-bit data, data valid on positive edge of sclk 110 - right justified, 20-bit data, data valid on positive edge of sclk 111 - reserved function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 25 through 30. it is recommended that the adc and the dac are configured for the same digital interface format. 76543210 reserved mclkdiv ratio1 ratio0 master dif2 dif1 dif0 00000000
CS42L50 20 ds544pp1 4.1.11 analog i/o control (address 03h) 4.1.12 left/right channel mute (mute) default = 0 0 - disabled 1 - enabled function: digital mute of the left and right adc channels. 4.1.13 soft ramp and zero cross enable (soft/zc) default = 11 00 - change volume immediately 01 - change volume at next zero cross time 10 - change volume in 1db steps 11 - change volume in 1db steps at every zero cross time function: soft ramp enable : soft ramp allows level changes, both muting and attenuation, to be implemented via an incremental ramp. digital volume control is ramped from the current level to the new level at a rate of 1/8 db per left/right clock period. analog volume control is ramped in 1 db steps every 8 left/right clock periods in single speed mode, and 1db every 16 left/right clock periods in double speed mode. zero cross enable : zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a tim- eout period of 512 sample periods in single speed mode or 1024 sample periods in double speed mode (approximately 10.7ms at 48khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp and zero cross enable : soft ramp and zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1 db steps and be implemented on a signal zero crossing. the level change will occur after a timeout period of 512 sample periods in single speed mode or 1024 sample periods in double speed mode (approximately 10.7 ms at 48khz sample rate) if the signal does not encounter a zero cross- ing. the zero cross function is independently monitored and implemented for each channel. 76543210 mutel muter szc1 szc0 reserved indvc l=r hpfreeze 00110000
CS42L50 ds544pp1 21 4.1.14 independent volume control enable (indvc) default = 0 0 - disabled 1 - enabled function: when this function is disabled, the ain_l and ain_r volume levels are controlled by the left and right volume control registers and the independent analog gain control registers are ignored. when this function is enabled, the volume levels are determined by both the volume control registers and the independent analog gain control registers. 4.1.15 left channel volume = right channel volume (l=r) default = 0 0 - disabled 1 - enabled function: when this function is disabled, the left channel volume is determined by the left channel volume control register and right channel volume is determined by the right channel volume control register. when enabled, the left and right channel volumes are determined by the left channel volume control reg- ister and the right channel volume control register is ignored. 4.1.16 high-pass filter freeze (hpfreeze) default = 0 0 - frozen 1 - enabled function: the high-pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. if the hpfreeze bit is taken low during normal operation, the current value of the dc offset is frozen and this dc offset will continue to be subtracted from the conversion result.
CS42L50 22 ds544pp1 4.1.17 volume control: left channel (address 04h) & right channel (address 05h) default = 0 (no attenuation) function: the volume control allows the user to alter the signal level in 1 db increments from +12 to -96 db, when the indvc bit is disabled. when indvc is enabled, the volume control can be altered in 1 db increments from 0 to -96db. volume settings are decoded as shown above, using a 2?s complement code. the vol- ume changes are implemented as dictated by the soft and zero cross bits in the analog i/o control reg- ister. all volume settings less than -96db are equivalent to muting the channel. 4.1.18 left/right analog gain (address 06h) default = 0 (no gain) function: the level of the left and right analog channels can be adjusted in 1db increments as dictated by the soft ramp and zero cross bits from 0 to +12db when routed through the pga via the ainmux bits. levels are decoded as shown above. levels above +12db are interpreted as +12db. 76543210 vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000 binary code decimal value volume setting 00001010 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db 76543210 lvol3 lvol2 lvol1 lvol0 rvol3 rvol2 rvol1 rvol0 00000000 binary code decimal value volume setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db
CS42L50 ds544pp1 23 4.1.19 clip detection status (address 07h) default = 0 (no clipping detected) function: the clip flags indicate when there is an over-range condition anywhere in the CS42L50 internal signal path. these bits are ?sticky?. they constantly monitor the adc signal path and are set to 1 when an over- range condition occurs. they are reset to 0 when read. 4.2 dac (address = 0010001) 4.2.1 power and muting control (address 01h) 4.2.2 auto-mute (amute) default = 1 0 - disabled 1 - enabled function: the digital-to-analog converter output will mute following the reception of 8192 consecutive audio sam- ples of static 0 or -1. a single sample of non-static data will release the mute. detection and muting is done independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. the muting function is affected, similar to volume control changes, by the soft and zero cross bits in the power and muting control register. 4.2.3 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross digital and analog 10 - ramped digital and analog 11 - reserved function: immediate change when immediate change is selected all level changes will take effect immediately in one step. zero cross digital and analog zero cross enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. the requested level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 76543210 reserved reserved reserved reserved reserved reserved clip_l clip_r 00000000 76543210 amute szc1 szc0 por pdnhp pdnln pdn cp_en 11010010
CS42L50 24 ds544pp1 ramped digital and analog soft ramp allows digital level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock pe- riods. analog level changes will occur in 1 db steps on a signal zero crossing. the analog level change will occur after a timeout period of 512 sample periods (10.7 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. note: ramped digital and analog is not available in double speed mode. 4.2.4 power down headphone amplifier (pdnhp) default = 0 0 - disabled 1 - enabled function: the headphone amplifier will independently enter a low-power state when this function is enabled. 4.2.5 power down line amplifier (pdnln) default = 0 0 - disabled 1 - enabled function: the line output amplifier will independently enter a low-power state when this function is enabled. 4.2.6 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire dac device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation will begin. 4.2.7 control port enable (cp_en) default = 0 0 - disabled 1 - enabled function: the dac will enter control port mode when this bit is enabled. this bit must be set prior to writing to the control port.
CS42L50 ds544pp1 25 4.2.8 channel a analog headphone attenuation control (address 02h) (hvola) 4.2.9 channel b analog headphone attenuation control (address 03h) (hvolb) default = 0 db (no attenuation) function: the analog headphone attenuation control operates independently from the digital volume control. the analog headphone attenuation control registers allow attenuation of the headphone output signal for each channel in 1 db increments from 0 to -25 db. attenuation settings are decoded using a 2?s comple- ment code, as shown in table 1 . the volume changes are implemented as dictated by the soft and zero cross bits in the power and muting control register. all volume settings greater than zero are interpreted as zero. note: the analog headphone attenuation only affects the headphone outputs. when set for levels greater than -10db, the actual attenuation deviates from the register setting by more than 1 db. 4.2.10 channel a digital volume control (address 04h) (dvola) 4.2.11 channel b digital volume control (address 05h) (dvolb) default = 0 db (no attenuation) function: the digital volume control registers allow independent control of the signal levels in 1 db increments from +18 to -96 db. volume settings are decoded using a 2?s complement code, as shown in table 2 . the volume changes are implemented as dictated by the soft and zero cross bits in the power and mut- ing control register. all volume settings less than -96 db are equivalent to muting the channel via the atapi bits (see section 4.46). note: the digital volume control affects both the line outputs and the headphone outputs. setting this register to values greater than +18 db will cause distortion in the audio outputs. 76543210 hvolx7 hvolx6 hvolx5 hvolx4 hvolx3 hvolx2 hvolx1 hvolx0 00000000 binary code decimal value volume setting 00000000 0 0 db 11110110 -10 -10 db 11110001 -15 -15 db table 1. example analog volume settings 76543210 dvolx7 dvolx6 dvolx5 dvolx4 dvolx3 dvolx2 dvolx1 dvolx0 00000000
CS42L50 26 ds544pp1 4.2.12 tone control (address 06h) 4.2.13 bass boost level (bb) default = 0 db (no bass boost) function: the level of the shelving bass boost filter is set by bass boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 3 . levels above +12 db are interpreted as +12 db. 4.2.14 treble boost level (tb) default = 0 db (no treble boost) function: the level of the shelving treble boost filter is set by treble boost level. the level can be adjusted in 1 db increments from 0 to +12 db of boost. boost levels are decoded as shown in table 4 . levels above +12 db are interpreted as +12 db. note: treble boost is not available in double speed mode. binary code decimal value volume setting 00001010 12 +12 db 00000111 7 +7 db 00000000 0 0 db 11000100 -60 -60 db 10100110 -90 -90 db table 2. example digital volume settings 76543210 bb3 bb2 bb1 bb0 tb3 tb2 tb1 tb0 00000000 binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 3. example bass boost settings
CS42L50 ds544pp1 27 4.2.15 mode control (address 07h) 4.2.16 bass boost corner frequency (bbcf) default = 00 00 - 50 hz 01 - 100 hz 10 - 200 hz 11 - reserved function: the bass boost corner frequency is user selectable as shown above. 4.2.17 treble boost corner frequency (tbcf) default = 00 00 - 2 khz 01 - 4 khz 10 - 7 khz 11 - reserved function: the treble boost corner frequency is user selectable as shown above. note: treble boost is not available in double speed mode. 4.2.18 channel a volume = channel b volume (a=b) default = 0 0 - disabled 1 - enabled function: the aouta/hp_a and aoutb/hp_b volume levels are independently controlled by the a and the b channel volume control bytes when this function is disabled. the volume on both aouta/hp_a and aoutb/hp_b are determined by the a channel attenuation and volume control bytes, and the b chan- nel bytes are ignored when this function is enabled. binary code decimal value boost setting 0000 0 0 db 0010 2 +2 db 1010 6 +6 db 1001 9 +9 db 1100 12 +12 db table 4. example treble boost settings 76543210 bbcf1 bbcf0 tbcf1 tbcf0 a=b dem1 dem0 vcbyp 00000000
CS42L50 28 ds544pp1 4.2.19 de-emphasis control (dem) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 31) note: de-emphasis is not available in double speed mode. 4.2.20 digital volume control bypass (vcbyp) default = 0 0 - disabled 1 - enabled function: the digital volume control section is bypassed when this function is enabled. this disables the digital vol- ume control, muting, bass boost, treble boost, limiting and atapi functions. the analog headphone at- tenuation control will remain functional. 4.2.21 volume and mixing control (address 0ah) 4.2.22 tone control mode (tc) default = 00 00 - all settings are taken from user registers 01 - 12 db of bass boost at 100 hz and 6 db of treble boost at 7 khz 10 - 8 db of bass boost at 100 hz and 4 db of treble boost at 7 khz 11 - 4 db of bass boost at 100 hz and 2 db of treble boost at 7 khz function: the tone control mode bits determine how the bass boost and treble boost features are configured. the user defined settings from the bass and treble boost level and corner frequency registers are used when these bits are set to ?00?. alternately, one of three pre-defined settings may be used. 4.2.23 tone control enable (tc_en) default = 0 0 - disabled 1 - enabled function: the bass boost and treble boost features are active when this function is enabled. 76543210 tc1 tc0 tc_en lim_en atapi3 atapi2 atapi1 atapi0 00001001
CS42L50 ds544pp1 29 4.2.24 atapi channel mixing and muting (atapi) default = 1001 - aouta/hp_a = l, aoutb/hp_b = r (stereo) function: the CS42L50 implements the channel mixing functions of the atapi cd-rom specification. refer to table 5 and figure 32 for additional information. note: all mixing functions occur prior to the digital volume control. 4.2.25 mode control 2 (address 0bh) 4.2.26 master clock divide enable (mclkdiv) default = 0 0 - disabled 1 - enabled function: the mclkdiv bit enables a circuit which divides the externally applied mclk signal by 2 prior to all other dac circuitry. 4.2.27 line amplifier gain compensation (line) default = 00 00 - 0.785 x va 01 - 0.943 x va 10 - reserved atapi3 atapi2 atapi1 atapi0 aouta/hp_a aoutb/hp_b 0000 mute mute 0001 mute r 0010 mute l 0011 mute [(l+r)/2] 0100 r mute 0101 r r 0110 r l 0111 r [(l+r)/2] 1000 l mute 1001 l r 1010 l l 1011 l [(l+r)/2] 1100[(l+r)/2] mute 1101[(l+r)/2] r 1110[(l+r)/2] l 1111[(l+r)/2] [(l+r)/2] table 5. atapi decode 76543210 mclkdiv line1 line0 reserved reserved dif2 dif1 dif0 00000000
CS42L50 30 ds544pp1 11 - line mute function: the line amplifier gain compensation bits allow the user to scale the full-scale line output level according to the power supply voltage used. the full-scale line output level will be equal to {gain factor}xva, where {gain factor} is selected from options above. the line mute option is available to allow muting of the line output when the headphone output is still in use and the line amp is still powered up. to use this feature, first mute the outputs via the atapi bits. next, set the line gain to line mute. finally, un-mute the outputs with the atapi bits. following these steps will ensure a click free mute. 4.2.28 digital interface format (dif) default = 000 - format 0 (i 2 s, up to 24-bit data) function: the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 25-30. it is recommended that the adc and the dac is configured for the same digital interface format. dif2 dif1 dif0 description format figure 000 i 2 s, up to 24-bit data 030 001 reserved -- 010 left justified, up to 24-bit data, 225 011 right justified, 24-bit data 327 100 right justified, 20-bit data 429 101 right justified, 16-bit data 526 110 right justified, 18-bit data 628 111 identical to format 0 030 table 6. digital interface format
CS42L50 ds544pp1 31 5. pin descriptions filter capacitor afltr rst reset filter capacitor afltl scl control port clock voltage reference filt+_adc sda control port data analog input 2 right ain_r2 lrck left/right clock analog input 2 left ain_l2 sdout serial audio data output ground reference ref_gnd va analog power analog input 1 right ain_r1 gnd ground reference analog input 1 left ain_l1 vl interface power quiescent voltage vq_adc sdin serial audio data input voltage reference filt+_dac mclk master clock quiescent voltage vq_dac sclk serial clock headphone a output hp_a mutec external mute control headphone amp power va_hp aoutl analog output left headphone b output hp_b aoutr analog output right 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 pin name # pin description va 23 analog power ( input ) - positive power supply for the analog section. refer to the recommended oper- ating conditions for appropriate voltages. vl 21 logic power ( input ) - determines the required signal level for the digital input/output. refer to the rec- ommended operating conditions for appropriate voltages. va_hp 13 headphone amp power ( input ) - positive power supply for the headphone amplifier. refer to the rec- ommended operating conditions for appropriate voltages. vq_adc vq_dac 9,11 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vq must be capacitively coupled to analog ground, as shown in the typical connection diagram. the nominal voltage level is specified in the analog characteristics and specifications section. vq presents an appreciable source impedance and any current drawn from this pin will alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc current is less than 10ua. ref_gnd 6 reference ground ( input ) - ground reference for the internal sampling circuits and must be connected to analog ground. gnd 22 ground ( input ) - ground reference. should be connected to analog ground. serial audio interface mclk 19 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. sclk 18 serial clock ( input / output ) - serial clock for the serial audio interface. lrck 25 left right clock ( input / output ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/right clock must be at the audio sample rate, fs. sdin 20 serial audio data input ( input ) - input for two?s complement serial audio data. sdout 24 serial audio data output ( output ) - output for two?s complement serial audio data.
CS42L50 32 ds544pp1 analog input/output ain_rx ain_lx 4, 5, 7,8 analog inputs ( input ) - the full scale analog input level is specified in the analog input characteristics specification table. aoutl aoutr 15, 16 analog outputs ( output ) - the full scale analog line output level is specified in the analog output char- acteristics specifications table. hp_a hp_b 12, 14 headphone outputs ( output ) - the full scale analog headphone output level is specified in the analog output characteristics specifications table. control port interface scl 27 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage as shown in the typical connection diagram. sda 26 serial control data ( input/output ) - sda is a data i/o line and requires an external pull-up resistor to the logic interface voltage, as shown in the typical connection diagram. control & misc. afltr afltl 1,2 anti-aliasing capacitors (output) - anti-aliasing capacitors for the left and right channels. an external capacitor is required from afltr and afltl to ground, as shown in the typical connections diagram. afltr and afltl are not intended to supply external current, and any current drawn from these pins will alter device performance. filt+_adc 3 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. requires the capacitive decoupling to agnd as shown in the typical connection diagram. filt+_dac 10 positive voltage reference ( output ) - positive reference voltage for the internal sampling circuits. requires the capacitive decoupling to agnd as shown in the typical connection diagram. mutec 17 mute control ( output ) - the mute control pin goes low during power-up initialization, reset, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect. this pin is intended to be used as a control for an external mute circuit to prevent the clicks and pops that can occur in any single supply system. the use of an external mute circuit is not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops. rst 28 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. when high, the control port becomes operational and the cp_en bits must be set and the pdn bits must be cleared before normal operation will occur. the control port cannot be accessed when reset is low.
CS42L50 ds544pp1 33 6. applications 6.1 grounding and power supply decoupling as with any high resolution converter, the CS42L50 requires careful attention to power sup- ply and grounding arrangements to optimize per- formance. figure 4 shows the recommended power arrangement with va, va_hp, and vl connected to clean supplies. decoupling capacitors should be located as close to the device package as possible. if desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be used on each supply pin. 6.2 clock modes the CS42L50 operates in one of two clocking modes. single speed mode supports input sample rates up to 50 khz, and double speed mode sup- ports input sample rates up to 100 khz. all clock modes use 64x oversampling. 6.3 ep73xx serial port interface special considerations must be made when inter- facing the CS42L50 with the ep73xx series of arm processors. to receive stereo data from the adc, connect the mclk pin (pin 19) of the CS42L50 to the buz pin (pin 93) of the ep73xx, and run the serial port in 64fs mode with mclk generation enabled on the ep73xx. any other con- figuration, either hardware or software modes, will result in mono data being produced from the adc of the CS42L50. 6.4 de-emphasis the CS42L50 includes on-chip digital de-empha- sis. figure 31 shows the de-emphasis curve. the frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, fs. the de-emphasis feature is included to accommo- date older audio recordings that utilize pre-empha- sis equalization as a means of noise reduction. 6.5 recommended power-up sequence 1) hold rst low until the power supply, master clock and left/right clock are stable. in this state, the control port is reset to its default set- tings and vq_adc and vq_dac will remain low. 2) bring rst high. the device will remain in a low power state and vq_adc and vq_dac remain low. the control port will be accessible at this time and the desired register settings can be loaded after setting the cp_en bits and while keeping the pdn bits set to 1. 3) once the registers are configured as desired, set the pdn bits to 0, initiating the power-up se- quence. 6.6 optional external headphone mute an external headphone mute circuit, as shown in the cdb42l50 datasheet schematic, is recom- mended to minimize the effects of output transients during power-up and power-down. this technique minimizes the audio transients commonly pro- duced by single-ended, single-supply converters when it is implemented with external dc-blocking capacitors connected in series with the audio out- puts. use of the mute control function on the line out- puts is recommended for designs requiring the ab- solute minimum in extraneous clicks and pops. also, use of the mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios only limited by the ex- ternal mute circuit. see the cdb42l50 datasheet for a suggested mute circuit. 7. control port interface the control port is used to load all the internal set- tings. the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference prob- lems, the control port pins should remain static if
CS42L50 34 ds544pp1 no operation is required. please note that the inter- nal registers are separated into two unique chip ad- dress blocks, one for the control of the adc and one for the control of the dac portion of the codec. sda is a bidirectional data line. data is clocked into and out of the part by the clock, scl, with the clock to data relationship as shown in figure 5. the upper 6 bits of the 7 bit address field must be 001000. to communicate with the CS42L50, the chip address should match that of the adc (0010000) or dac (0010001) address. the eighth bit of the address byte is the r/w bit (high for a read, low for a write). if the operation is a write, the next byte is the memory address pointer, map, which selects the register to be read or written. the map is then followed by the data to be written. if the operation is a read, the contents of the register pointed to by the map will be output after the chip address. the CS42L50 has map auto increment capability, enabled by the incr bit in the map register. if incr is 0, then the map will stay constant for suc- cessive writes. if incr is set to 1, then map will auto increment after each byte is written, allowing block reads or writes of successive registers.
CS42L50 ds544pp1 35 7.1 memory address pointer (map) 7.2 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 7.3 map0-3 (memory address pointer) default = ?0000? 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 sda scl 001000 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the m em ory a ddress pointer, m ap. note 1 figure 5. control port timing
CS42L50 36 ds544pp1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.42 0. 44 0.46 0. 48 0. 5 0. 52 0.54 0. 56 0. 58 0. 6 frequency (normalized to fs) amplitude db figure 6. decimation filter single speed stopband rejection figure 7. decimation filter single speed transition band -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0. 05 0.1 0. 15 0.2 0. 25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0. 45 0. 46 0. 47 0. 48 0.49 0.5 0. 51 0. 52 0. 53 0. 54 0. 55 frequency (normalized to fs) amplitude db figure 8. decimation filter single speed transition band (detail) figure 9. decimation filter single speed passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 frequency (normalized to fs) amplitude db figure 10. decimation filter double speed stopband rejection figure 11. decimation filter double speed transition band
CS42L50 ds544pp1 37 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude db -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 12. decimation filter double speed transition band (detail) figure 13. decimation filter double speed passband ripple
CS42L50 38 ds544pp1 figure 14. interpolation filter single speed stopband rejection figure 15. interpolation filter single speed transition band figure 16. interpolation filter single speed transition band (detail) figure 17. interpolation filter single speed passband ripple -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.6 0 frequency (normalized to fs) amplitude db figure 18. interpolation filter double speed stopband rejection figure 19. interpolation filter double speed transition band
CS42L50 ds544pp1 39 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.5 5 frequency (normalized to fs) amplitude db -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.5 0 frequency (normalized to fs) amplitude db figure 20. interpolation filter double speed transition band (detail) figure 21. interpolation filter double speed passband ripple gnd ain_xx 150 ? 0.47 f 0.01 f figure 22. line input test circuit
CS42L50 40 ds544pp1 aoutx agnd 3.3 f v out r l c l + figure 23. line output test load hp_x agnd 220 f v out r l c l + figure 24. headphone output test load
CS42L50 ds544pp1 41 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 left justified, up to 24-bit data. data valid on rising edge of sclk. figure 25. left justified, up to 24-bit data lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks right justified, 16-bit data. data valid on rising edge of sclk. sclk must have at least 32 cycles per lrck period. figure 26. right justified, 16-bit data lrck sclk left channel sdata 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel right justified, 24-bit data. data valid on rising edge of sclk. sclk must have at least 48 cycles per lrck period. figure 27. right justified, 24-bit data
CS42L50 42 ds544pp1 lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 28. right justified, 18-bit data right justified, 18-bit data. data valid on rising edge of sclk. sclk must have at least 36 cycles per lrck period. lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 right justified, 20-bit data. data valid on rising edge of sclk. sclk must have at least 40 cycles per lrck period. figure 29. right justified, 20-bit data lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 i 2 s, up to 24-bit data. data valid on rising edge of sclk figure 30. i 2 s, up to 24-bit data
CS42L50 ds544pp1 43 gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 31. de-emphasis curve volume control aouta/hp_a aoutb/hp_b left channel audio data right channel audio data volume control mute mute eq eq digital a channel digital b channel figure 32. atapi block diagram
CS42L50 44 ds544pp1 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 9. references 1) "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 1) "the i 2 c-bus specification: version 2.1" philips semiconductors, january 2000. http://semiconductors.philips.com
CS42L50 ds544pp1 45 10. package dimensions figure 33. package dimensions
CS42L50 46 ds544pp1 figure 34. package top and side views
CS42L50 ds544pp1 47 figure 35. package bottom view

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